Memory components such as one time programmable memories, registers, ROM, RAM, flash memory, etc., are used within a wide variety of digital circuitries. When these memories are used within low power applications, various types of problems often arise. One problem involves the large static current required by memories. The static current varies depending upon the output word maintained on the outputs of the memories. In this situation, the static currents used by the memory can vary anywhere from 1 milliamp to 1.5 milliamps. Due to the large static currents, the memories require higher device powers than are desired, particularly when the system clock associated with the memory slows toward 0 Hz.
One solution to this problem has been to turn off the memory devices to save power when they are in a non active state. However, when a memory is turned off, additional problems arise due to the long time the memory devices take to power up relative to the system clock. Many memories such as one time programmable memories may have a turn on time of approximately 300 nanoseconds. Thus, there is a need for an improved solution to memory power control within low power devices that limits the power usage of the memory when not in use, yet sufficiently addresses the long turn on times associated with the memories.